This invention relates to integrated circuit devices such as field-programmable gate arrays (“FPGAs”), and more particularly to circuitry on FPGAs that can be used to transmit and/or receive data signals in multiple channels.
An integrated circuit such as an FPGA may be provided with multiple channels of circuitry for transmitting and/or receiving data signals. These channels may be grouped into several groups of channels. Each group may receive a reference clock signal. For greater flexibility of use of the circuitry, it may be desirable to be able to use the reference clock signal received by any of the groups in that group and/or in any other(s) of the groups. Any such distribution or sharing of clock signals among the groups is preferably done as efficiently as possible. This is aided by performing the clock signal distribution within the circuitry of the groups. It is also desirable for the circuitry of all of the groups to be the same or substantially the same, e.g., because this facilitates design and verification. And it is desirable for the groups to be as close together as possible, e.g., to conserve “real estate” on the integrated circuit, to avoid interconnections that are longer than necessary, etc. Improved clock interconnection or distribution circuitry that will help satisfy criteria such as these is needed.